A major cost in semiconductor production is the development and maintenance of test programs that test integrated circuits for viability and functionality. This activity usually entails many hours of work on the actual tester hardware. However, existing semiconductor testers have little or no capability for simulating test programs, except for checking the semantics of the test programming language. This limitation forces engineers to debug their test programs on the actual tester hardware. But using tester hardware for test program development is not a cost-effective use of the expensive test equipment. Besides, since a tester is usually shared among groups of engineers, the amount of time allocated to use the tester is limited, which creates a bottleneck in the development of test programs, resulting in a process where development occurs serially. Such limitations in test program development may delay production of the integrated circuits, which could delay product release and lost market opportunities.
Therefore, there is a need for a method and system for verifying test program functionality without using expensive test equipment. In particular, there is a need for a method and system for simulating a modular test system with test programs, vendor modules, and their corresponding device-under-tests (DUTs).
An objective of the present invention is to reduce the amount of use of tester hardware for test program development, thereby optimizing the use of the valuable tester equipment. Another objective of the present invention is to identify problems in the test programs, modules and DUTs before they are run on the tester equipment. Yet another objective of the present invention is to provide an environment for parallel development of test programs, modules, and DUTs, thereby reducing the overall product development time.